DBT 2007 - Call for Papers

CALL FOR PAPERS & PARTICIPATION

Overview -- Submissions -- Additional Information -- Committees

Overview

THEME
Process Variations + Systematic Defects: Can DBT Help?

As we push deeper into nanometer technologies, systematic defects are outstretching random defects as the dominant yield limiter and are presenting unique challenges to the yield enhancement community. New methodologies are required to detect, monitor, and resolve systematic defect mechanisms at the 90nm technology node and below. As mainstream silicon manufacturing processes scale to and beyond the 65-nm node, we also find the mean and variance of process variations increasing. Fallout caused by systematic defects is obfuscated by process variations, making them more difficult to distinguish using traditional testing methods. This year's workshop is charged with determining whether defect-based test is better positioned to provide information regarding root cause, and whether such methods can help with the identification and isolation of systematic defects.

The IEEE International Workshop on Current and Defect Based Testing (DBT 2007) is aimed at addressing these issues and others related to this year’s theme “Process Variations + Systematic Defects: Can DBT Help?” Paper presentations on topics related to the workshop’s theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

The workshop includes (but is not limited to) the following topics:

Test Data Analysis
Transition and Delay Testing
IDDQ and IDDT Testing
Low voltage Testing
Noise and Cross-talk Testing
Defect Coverage & Metrics
Economics of Defect Based Testing
Data-Mining approaches for Test Data Processing
Elevated Voltage Testing and Stress Testing
Reliability and Yield
Nanometer Test Challenges
Mixed Current/Voltage Testing
Fault Localization & Diagnosis
Data-Based Testing

Submissions

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To present at the workshop, submit a postscript or Acrobat (PDF) version of an extended abstract of at least 1000 words via E-mail to the Program Chair by Aug. 18, 2007. Each submission should include full name and address of each author, affiliation, telephone number, FAX and E-mail address. The presenter should also be identified. Camera-ready papers for inclusion in the digest of papers will be due on Oct. 6, 2007. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.

Submission deadline: August 18, 2007
Acceptance Notification: September 15, 2007
Camera Ready: October 6 , 2007

Technical Program Submission:

Mohammad Tehranipoor
Program Chair
Electrical & Computer Engineering
University of Connecticut
Storrs, CT-06269, USA
Tel: (860) 486-3471, x-2447(FAX)
E-mail: tehrani@engr.uconn.edu

Additional Information

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General Information

Hans Manhaeve
General Chair
Q-Star Test
L.Bauwensstraat 20
Bruegge, Belgium
Tel: +32 50 319273. +32 50 312350(FAX)
E-mail: Hans.Manhaeve@qstar.be

Committees

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Co-General Chair

Mehdi Tahoori
Northeastern University, USA

Vice General Chair

Sankaran Menon
Intel Corporation, USA

Program Chair

Mohammad Tehranipoor
Univ. of Connecticut, USA

Vice-Program Chair

Jim Plusquellic
Univ. of Maryland, Baltimore County, USA

Finance Chair

Sankaran M. Menon
Intel Corporation, USA

Publicity Chair

Jaume Segura
UIB Baleares, Spain

Advisor

Charles Hawkins
University of New Mexico, USA

Steering Committee

Yashwant K. Malaiya (Chair), Colorado State University, USA
Anura Jayasumana C ol State Univ, USA
Joan Figueras, UPC, Barcelona, Spain
Adit Singh, Auburn University, USA
Duncan (Hank) Walker, Texas A&M Univ.

Program Committee

Robert Aitken, ARM, USA
Subhasish Mitra, Stanford Univ., USA
Chintan Patel, UMBC, USA
Jerry Soden, Sandia National Labs, USA
Michel Renovell, LIRMM, France
Krish Chakrabarty, Duke Univ., USA
Claude Thibeault,Ecole de Tech Sup,Canada
Sreejit Chakravarty, LSI Logic, USA
Martin Margala, U-Mass, USA
Sule Ozev, Duke University
Xiaoqing Wen (Kyushu Institute of Technology)
Shawn Blanton, CMU, USA
Anuja Sehgal, AMD
Sagar Sabade, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Robert Daasch, Portland State Univ.
Rajesh Raina, Freescale, USA
Geir Eide, Magma, USA
Manoj Sachdev, Univ. of Waterloo, Canada
Anne Gattiker, IBM, USA
Tom Bartenstein, Cadence, USA

For more information, visit us on the web at: http://dbt.tttc-events.org/

IEEE International Workshop On Current & Defect Based Testing is sponsored by the IEEE Computer Society TC on Test Technology.